/*
 * Copyright 2016 Broadcom Corporation.
 *
 * SPDX-License-Identifier:      GPL-2.0+
 */

#ifndef __SOCREGS_H
#define __SOCREGS_H

#define ChipcommonA_ChipID 0x18000000
#define ICFG_CHIP_ID_REG   ChipcommonA_ChipID
#define ChipcommonB_PWMCTL 0x18031000
#define ChipcommonB_WDT_WDOGLOAD 0x18039000
#define ChipcommonB_GP_DATA_IN 0x18030000
#define ChipcommonB_GP_AUX_SEL_BASE 0x028
#define ChipcommonB_SMBus_Config 0x18038000
#define QSPI_mspi_SPCR0_LSB 0x18027200
#define QSPI_mspi_DISABLE_FLUSH_GEN 0x18027384
#define QSPI_bspi_registers_REVISION_ID 0x18027000
#define QSPI_bspi_registers_BSPI_PIO_DATA 0x1802704c
#define QSPI_raf_START_ADDR 0x18027100
#define QSPI_raf_interrupt_LR_fullness_reached 0x180273a0
#define QSPI_mspi_interrupt_MSPI_halt_set_transaction_done 0x180273b8
#define QSPI_IDM_IDM_IO_CONTROL_DIRECT 0x1811c408
#define QSPI_raf_CURR_ADDR 0x18027120
#define CRU_control 0x1803e000
#define DMU_CRU_RESET 0x1803f200
#define GMAC0_DEVCONTROL 0x18022000
#define GMAC1_DEVCONTROL 0x18023000
#define ChipcommonA_GPIOEvent_BASE 0x078
#define ChipcommonA_GPIOInput_BASE 0x060
#define ChipcommonB_GP_INT_CLR_BASE 0x024
#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
#define ChipcommonA_GPIOInput_BASE 0x060
#define ChipcommonB_GP_INT_MSK_BASE 0x018
#define ChipcommonA_GPIOIntMask_BASE 0x074
#define ChipcommonB_GP_INT_MSK_BASE 0x018
#define ChipcommonA_GPIOEventIntMask_BASE 0x07c
#define ChipcommonB_GP_INT_MSTAT_BASE 0x020
#define ChipcommonA_GPIOEventIntPolarity_BASE 0x084
#define ChipcommonA_IntStatus_BASE 0x020
#define ChipcommonA_GPIOIntPolarity_BASE 0x070
#define ChipcommonA_IntStatus_BASE 0x020
#define ChipcommonB_GP_INT_DE_BASE 0x010
#define ChipcommonB_GP_INT_EDGE_BASE 0x014
#define ChipcommonB_GP_INT_TYPE_BASE 0x00c
#define ChipcommonA_GPIOIntPolarity_BASE 0x070
#define ChipcommonB_GP_AUX_SEL_BASE 0x028
#define ChipcommonB_GP_PAD_RES_BASE 0x034
#define ChipcommonB_GP_RES_EN_BASE 0x038
#define ChipcommonA_ChipID 0x18000000
#define DMAC_pl330_DS 0x18020000
#define ChipcommonA_GPIOInput 0x18000060
#define ChipcommonB_GP_DATA_IN 0x18030000
#define PAXB_0_CLK_CONTROL 0x18012000
#define PAXB_0_CONFIG_IND_ADDR_BASE 0x120
#define ChipcommonB_MII_Management_Control 0x18032000
#define NAND_nand_flash_REVISION 0x18026000
#define NAND_direct_read_rd_miss 0x18026f00
#define NAND_IDM_IDM_IO_CONTROL_DIRECT 0x1811b408
#define ChipcommonB_PWM_PERIOD_COUNT0_BASE 0x004
#define ChipcommonB_PWM_PRESCALE_BASE 0x024
#define ChipcommonB_PWM_PERIOD_COUNT1_BASE 0x00c
#define ChipcommonB_PWM_PERIOD_COUNT2_BASE 0x014
#define ChipcommonB_PWM_PERIOD_COUNT3_BASE 0x01c
#define ChipcommonB_PWM_DUTYHI_COUNT0_BASE 0x008
#define ChipcommonB_PWM_DUTYHI_COUNT1_BASE 0x010
#define ChipcommonB_PWM_DUTYHI_COUNT2_BASE 0x018
#define ChipcommonB_PWM_DUTYHI_COUNT3_BASE 0x020
#define ChipcommonB_PWMCTL_BASE 0x000
#define ChipcommonB_rng_CTRL 0x18033000
#define DMU_CRU_RESET_BASE 0x200
#define ChipcommonB_SMBus1_SMBus_Config 0x1803b000
#define DMU_PCU_IPROC_STRAPS_CAPTURED_BASE 0x028
#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_boot_dev_R 9
#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_type_R 5
#define DMU_PCU_IPROC_STRAPS_CAPTURED__strap_nand_page_R 3
#define ChipcommonA_IntMask_BASE 0x024
#define DMU_PCU_CRU_RESET_REASON 0x1803f014
#define DMU_PCU_CRU_RESET_REASON__watchdog_reset 0
#define ChipcommonA_GPIOOut 0x18000064
#define ChipcommonA_GPIOOutEn 0x18000068
#define AMAC_IDM0_IO_CONTROL_DIRECT 0x18110408
#define AMAC_IDM0_IO_CONTROL_DIRECT__CLK_250_SEL 6
#define AMAC_IDM0_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
#define AMAC_IDM0_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
#define AMAC_IDM1_IO_CONTROL_DIRECT 0x18111408
#define AMAC_IDM1_IO_CONTROL_DIRECT__CLK_250_SEL 6
#define AMAC_IDM1_IO_CONTROL_DIRECT__DIRECT_GMII_MODE 5
#define AMAC_IDM1_IO_CONTROL_DIRECT__DEST_SYNC_MODE_EN 3
#define IPROC_WRAP_USBPHY_CTRL 0x1803fc34
#define IPROC_WRAP_GEN_PLL_STATUS__GEN_PLL_LOCK 0
#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_R 0
#define IPROC_WRAP_GEN_PLL_CTRL1__NDIV_INT_WIDTH 10
#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_R 10
#define IPROC_WRAP_GEN_PLL_CTRL1__PDIV_WIDTH 3
#define IPROC_WRAP_GEN_PLL_CTRL1__CH0_MDIV_R 13
#define IPROC_WRAP_GEN_PLL_CTRL1__CH1_MDIV_R 21
#define IPROC_WRAP_GEN_PLL_CTRL2__CH2_MDIV_R 0
#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_R 8
#define IPROC_WRAP_GEN_PLL_CTRL2__CH4_MDIV_R 16
#define IPROC_WRAP_MISC_CONTROL 0x1803fc3c
#define DMU_CRU_RESET										0x1803f200
#define IPROC_WRAP_IPROC_XGPLL_CTRL_3						0x1803fc28
#define IPROC_WRAP_IPROC_XGPLL_STATUS						0x1803fc30
#define IPROC_WRAP_GEN_PLL_CTRL0							0x1803fc00
#define IPROC_WRAP_GEN_PLL_CTRL0__FAST_LOCK					28
#define IPROC_WRAP_GEN_PLL_CTRL1							0x1803fc04
#define IPROC_WRAP_GEN_PLL_CTRL2							0x1803fc08
#define IPROC_WRAP_GEN_PLL_CTRL3							0x1803fc0c
#define IPROC_WRAP_GEN_PLL_CTRL3__SW_TO_GEN_PLL_LOAD		28
#define IPROC_WRAP_GEN_PLL_CTRL3__LOAD_EN_CH_R				16
#define IPROC_WRAP_GEN_PLL_CTRL2__CH3_MDIV_WIDTH			8
#define IPROC_WRAP_GEN_PLL_STATUS							0x1803fc18
#define ChipcommonA_CoreCtrl								0x18000008
#define ChipcommonA_CoreCtrl__UARTClkOvr					0
#define APBW_IDM_IDM_IO_CONTROL_DIRECT						0x18131408
#define APBW_IDM_IDM_IO_CONTROL_DIRECT__UARTClkSel			17
#define ChipcommonA_ClkDiv									0x180000a4
#define ChipcommonA_ClkDiv__UartClkDiv_R					0
#define ChipcommonA_ClkDiv__UartClkDiv_WIDTH				8
#define CRU_ihost_pwrdwn_en									0x1803e004
#define CRU_ihost_pwrdwn_en__logic_pwrdown_neon1			13
#define CRU_ihost_pwrdwn_en__logic_pwrdown_neon1_WIDTH		1
#define CRU_ihost_pwrdwn_en__logic_clamp_on_neon1			12
#define CRU_ihost_pwrdwn_en__logic_clamp_on_neon1_WIDTH		1
#define CRU_ihost_pwrdwn_en__logic_pwrdown_neon0			5
#define CRU_ihost_pwrdwn_en__logic_pwrdown_neon0_WIDTH		1
#define CRU_ihost_pwrdwn_en__logic_clamp_on_neon0			4
#define CRU_ihost_pwrdwn_en__logic_clamp_on_neon0_WIDTH		1
#define CRU_ihost_pwrdwn_en__logic_clamp_on_cpu1			8
#define CRU_ihost_pwrdwn_en__ram_clamp_on_cpu1				10
#define CRU_ihost_pwrdwn_status								0x1803e008
#define CRU_cpu0_powerdown									0x1803e00c
#define CRU_cpu0_powerdown__start_cpu0_powerdown_seq		31
#define CRU_ihost_pwrdwn_en__logic_pwrdown_cpu1				9
#define CRU_ihost_pwrdwn_en__ram_pwrdown_cpu1				11
#define IPROC_WRAP_IPROC_XGPLL_CTRL_4						0x1803fc2c
#define IPROC_WRAP_IPROC_XGPLL_CTRL_2						0x1803fc24
#define IPROC_WRAP_IPROC_XGPLL_CTRL_0						0x1803fc1c
#define IPROC_WRAP_IPROC_XGPLL_CTRL_1_RESETVALUE			0x660c000
#define IPROC_WRAP_IPROC_XGPLL_CTRL_1						0x1803fc20
#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__SW_OVWR				27
#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__POST_RESETB			26
#define IPROC_WRAP_IPROC_XGPLL_CTRL_1__RESETB				25
#define IPROC_WRAP_IPROC_XGPLL_STATUS__IPROC_WRAP_XGPLL_LOCK 31
#define DDR_DENALI_CTL_00									0x18010000
#define DDR_DENALI_CTL_89									0x18010164
#define DDR_DENALI_CTL_43									0x180100ac
#define DDR_S1_IDM_RESET_CONTROL							0x18109800
#define DDR_S2_IDM_RESET_CONTROL							0x1810a800
#define DDR_PHY_CONTROL_REGS_REVISION						0x18010800
#define DDR_PHY_CONTROL_REGS_STRAP_CONTROL					0x180108b0
#define DDR_PHY_CONTROL_REGS_STRAP_CONTROL2					0x180108b4
#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS					0x1801081c
#define DDR_PHY_CONTROL_REGS_PLL_CONFIG						0x18010814
#define DDR_PHY_CONTROL_REGS_PLL_STATUS						0x18010810
#define DDR_PHY_WORD_LANE_0_READ_DATA_DLY					0x18010b60
#define DDR_PHY_WORD_LANE_0_WR_PREAMBLE_MODE				0x18010bac
#define DDR_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL				0x1801083c
#define DDR_PHY_CONTROL_REGS_VDL_CALIBRATE					0x18010848
#define DDR_PHY_CONTROL_REGS_VDL_CALIB_STATUS				0x1801084c
#define DDR_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL				0x18010834
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W				0x18010a04
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W			0x18010a10
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W			0x18010a14
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W			0x18010a18
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W			0x18010a1c
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W			0x18010a20
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W			0x18010a24
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W			0x18010a28
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W			0x18010a2c
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W			0x18010a30
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W				0x18010aa4
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W			0x18010ab0
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W			0x18010ab4
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W			0x18010ab8
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W			0x18010abc
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W			0x18010ac0
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W			0x18010ac4
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W			0x18010ac8
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W			0x18010acc
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W			0x18010ad0
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P			0x18010a08
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N			0x18010a0c
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P			0x18010aa8
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N			0x18010aac
#define DDR_DENALI_CTL_213									0x18010354
#define DDR_BistConfig										0x18010400
#define DDR_BistGeneralConfigurations						0x18010408
#define DDR_BistConfigurations								0x1801040c
#define DDR_BistConfigurations__ConsAddr8Banks				21
#define DDR_BistConfigurations__ReadWeight_R				8
#define DDR_BistConfigurations__WriteWeight_R				0
#define DDR_BistStartAddress								0x18010414
#define DDR_BistEndAddress									0x18010418
#define DDR_BistEndAddress__BistEndAddress_WIDTH			26
#define DDR_BistNumberOfActions								0x18010410
#define DDR_BistPatternWord0								0x1801043c
#define DDR_BistPatternWord1								0x18010438
#define DDR_BistPatternWord2								0x18010434
#define DDR_BistPatternWord3								0x18010430
#define DDR_BistPatternWord4								0x1801042c
#define DDR_BistPatternWord5								0x18010428
#define DDR_BistPatternWord6								0x18010424
#define DDR_BistPatternWord7								0x18010420
#define DDR_BistConfigurations__IndWrRdAddrMode				19
#define DDR_BistConfigurations__BistEn						25
#define DDR_S1_IDM_RESET_CONTROL							0x18109800
#define DDR_S2_IDM_RESET_CONTROL							0x1810a800
#define DDR_PHY_CONTROL_REGS_REVISION						0x18010800
#define ROM_S0_IDM_IO_STATUS								0x1811a500
#define DDR_S1_IDM_IO_STATUS								0x18109500
#define DDR_S1_IDM_IO_CONTROL_DIRECT						0x18109408
#define DDR_BistStatuses									0x18010460
#define DDR_BistStatuses__BistFinished						0
#define DDR_BistErrorOccurred								0x1801046c
#define PAXB_0_CONFIG_IND_ADDR								0x18012120
#define PAXB_0_CONFIG_IND_DATA								0x18012124
#define DDR_BistConfig__axi_port_sel						1
#define DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN			0x18010a00
#define NAND_nand_flash_INTFC_STATUS						0x18026014
#define NAND_ro_ctlr_ready									0x18026f10
#define NAND_nand_flash_CMD_ADDRESS							0x1802600c
#define NAND_nand_flash_CMD_EXT_ADDRESS						0x18026008
#define NAND_nand_flash_INIT_STATUS							0x18026144
#define NAND_nand_flash_FLASH_DEVICE_ID						0x18026194
#define NAND_nand_flash_ONFI_STATUS							0x18026148
#define NAND_nand_flash_CONFIG_CS1							0x18026064
#define NAND_nand_flash_CONFIG_CS0							0x18026054
#define NAND_nand_flash_ACC_CONTROL_CS1						0x18026060
#define NAND_nand_flash_ACC_CONTROL_CS0						0x18026050
#define NAND_nand_flash_FLASH_CACHE0						0x18026400
#define NAND_nand_flash_UNCORR_ERROR_COUNT                  0x180260fc
#define NAND_nand_flash_CORR_ERROR_COUNT                    0x18026100
#define NAND_nand_flash_ECC_CORR_EXT_ADDR                   0x1802610c
#define NAND_nand_flash_ECC_CORR_ADDR                       0x18026110
#define NAND_nand_flash_ECC_UNC_ADDR						0x18026118
#define NAND_nand_flash_CS_NAND_SELECT						0x18026018
#define NAND_nand_flash_SPARE_AREA_READ_OFS_0				0x18026200
#define NAND_nand_flash_SPARE_AREA_WRITE_OFS_0				0x18026280
#define NAND_nand_flash_FLASH_DEVICE_ID_EXT					0x18026198
#define NAND_nand_flash_CMD_START							0x18026004
#define NAND_IDM_IDM_RESET_CONTROL							0x1811b800
#define DMU_PCU_IPROC_STRAPS_CAPTURED						0x1803f028
#define DDR_PHY_ECC_LANE_READ_FIFO_STATUS					0x18010f90
#define AMAC_IDM0_IDM_RESET_CONTROL							0x18110800
#define AMAC_IDM1_IDM_RESET_CONTROL							0x18111800
#define ChipcommonB_MII_Management_Control					0x18032000
#define ChipcommonB_MII_Management_Command_Data				0x18032004
#define ChipcommonB_MII_Management_Control__BSY				8
#define ChipcommonB_MII_Management_Control__PRE				7
#define ChipcommonB_MII_Management_Control__EXT				9
#define ChipcommonB_MII_Management_Command_Data__SB_R		30
#define ChipcommonB_MII_Management_Command_Data__PA_R		23
#define ChipcommonB_MII_Management_Command_Data__RA_R		18
#define ChipcommonB_MII_Management_Command_Data__TA_R		16
#define ChipcommonB_MII_Management_Command_Data__OP_R		28
#define CMIC_DEV_REV_ID										0x48010224

#define IHOST_S1_IDM_ERROR_LOG_CONTROL 0x18107900
#define IHOST_S1_IDM_ERROR_LOG_COMPLETE 0x18107904
#define IHOST_S1_IDM_ERROR_LOG_STATUS 0x18107908
#define IHOST_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810790c
#define IHOST_S1_IDM_ERROR_LOG_ID 0x18107914
#define IHOST_S1_IDM_ERROR_LOG_FLAGS 0x1810791c
#define IHOST_S1_IDM_INTERRUPT_STATUS 0x18107a00
#define IHOST_S0_IDM_ERROR_LOG_CONTROL 0x18108900
#define IHOST_S0_IDM_ERROR_LOG_COMPLETE 0x18108904
#define IHOST_S0_IDM_ERROR_LOG_STATUS 0x18108908
#define IHOST_S0_IDM_ERROR_LOG_ADDR_LSB 0x1810890c
#define IHOST_S0_IDM_ERROR_LOG_ID 0x18108914
#define IHOST_S0_IDM_ERROR_LOG_FLAGS 0x1810891c
#define IHOST_S0_IDM_INTERRUPT_STATUS 0x18108a00
#define DDR_S1_IDM_ERROR_LOG_CONTROL 0x18109900
#define DDR_S1_IDM_ERROR_LOG_COMPLETE 0x18109904
#define DDR_S1_IDM_ERROR_LOG_STATUS 0x18109908
#define DDR_S1_IDM_ERROR_LOG_ADDR_LSB 0x1810990c
#define DDR_S1_IDM_ERROR_LOG_ID 0x18109914
#define DDR_S1_IDM_ERROR_LOG_FLAGS 0x1810991c
#define DDR_S1_IDM_INTERRUPT_STATUS 0x18109a00
#define DDR_S2_IDM_ERROR_LOG_CONTROL 0x1810a900
#define DDR_S2_IDM_ERROR_LOG_COMPLETE 0x1810a904
#define DDR_S2_IDM_ERROR_LOG_STATUS 0x1810a908
#define DDR_S2_IDM_ERROR_LOG_ADDR_LSB 0x1810a90c
#define DDR_S2_IDM_ERROR_LOG_ID 0x1810a914
#define DDR_S2_IDM_ERROR_LOG_FLAGS 0x1810a91c
#define DDR_S2_IDM_INTERRUPT_STATUS 0x1810aa00
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810b900
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810b904
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810b908
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810b90c
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID 0x1810b914
#define AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810b91c
#define AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS 0x1810ba00
#define CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810d900
#define CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810d904
#define CMICD_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810d908
#define CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810d90c
#define CMICD_S0_IDM_IDM_ERROR_LOG_ID 0x1810d914
#define CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810d91c
#define CMICD_S0_IDM_IDM_INTERRUPT_STATUS 0x1810da00
#define APBY_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1810f900
#define APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1810f904
#define APBY_S0_IDM_IDM_ERROR_LOG_STATUS 0x1810f908
#define APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1810f90c
#define APBY_S0_IDM_IDM_ERROR_LOG_ID 0x1810f914
#define APBY_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1810f91c
#define APBY_S0_IDM_IDM_INTERRUPT_STATUS 0x1810fa00
#define ROM_S0_IDM_ERROR_LOG_CONTROL 0x1811a900
#define ROM_S0_IDM_ERROR_LOG_COMPLETE 0x1811a904
#define ROM_S0_IDM_ERROR_LOG_STATUS 0x1811a908
#define ROM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1811a90c
#define ROM_S0_IDM_ERROR_LOG_ID 0x1811a914
#define ROM_S0_IDM_ERROR_LOG_FLAGS 0x1811a91c
#define ROM_S0_IDM_INTERRUPT_STATUS 0x1811aa00
#define NAND_IDM_IDM_ERROR_LOG_CONTROL 0x1811b900
#define NAND_IDM_IDM_ERROR_LOG_COMPLETE 0x1811b904
#define NAND_IDM_IDM_ERROR_LOG_STATUS 0x1811b908
#define NAND_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811b90c
#define NAND_IDM_IDM_ERROR_LOG_ID 0x1811b914
#define NAND_IDM_IDM_ERROR_LOG_FLAGS 0x1811b91c
#define NAND_IDM_IDM_INTERRUPT_STATUS 0x1811ba00
#define QSPI_IDM_IDM_ERROR_LOG_CONTROL 0x1811c900
#define QSPI_IDM_IDM_ERROR_LOG_COMPLETE 0x1811c904
#define QSPI_IDM_IDM_ERROR_LOG_STATUS 0x1811c908
#define QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811c90c
#define QSPI_IDM_IDM_ERROR_LOG_ID 0x1811c914
#define QSPI_IDM_IDM_ERROR_LOG_FLAGS 0x1811c91c
#define QSPI_IDM_IDM_INTERRUPT_STATUS 0x1811ca00
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL 0x1811d900
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x1811d904
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS 0x1811d908
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1811d90c
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_ID 0x1811d914
#define A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1811d91c
#define A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS 0x1811da00
#define SRAM_S0_IDM_ERROR_LOG_CONTROL 0x18120900
#define SRAM_S0_IDM_ERROR_LOG_COMPLETE 0x18120904
#define SRAM_S0_IDM_ERROR_LOG_STATUS 0x18120908
#define SRAM_S0_IDM_ERROR_LOG_ADDR_LSB 0x1812090c
#define SRAM_S0_IDM_ERROR_LOG_ID 0x18120914
#define SRAM_S0_IDM_ERROR_LOG_FLAGS 0x1812091c
#define SRAM_S0_IDM_INTERRUPT_STATUS 0x18120a00
#define APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL 0x18121900
#define APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE 0x18121904
#define APBZ_S0_IDM_IDM_ERROR_LOG_STATUS 0x18121908
#define APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1812190c
#define APBZ_S0_IDM_IDM_ERROR_LOG_ID 0x18121914
#define APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS 0x1812191c
#define APBZ_S0_IDM_IDM_INTERRUPT_STATUS 0x18121a00
#define AXIIC_DS_3_IDM_ERROR_LOG_CONTROL 0x18123900
#define AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE 0x18123904
#define AXIIC_DS_3_IDM_ERROR_LOG_STATUS 0x18123908
#define AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB 0x1812390c
#define AXIIC_DS_3_IDM_ERROR_LOG_ID 0x18123914
#define AXIIC_DS_3_IDM_ERROR_LOG_FLAGS 0x1812391c
#define AXIIC_DS_3_IDM_INTERRUPT_STATUS 0x18123a00
#define APBW_IDM_IDM_ERROR_LOG_CONTROL 0x18131900
#define APBW_IDM_IDM_ERROR_LOG_COMPLETE 0x18131904
#define APBW_IDM_IDM_ERROR_LOG_STATUS 0x18131908
#define APBW_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813190c
#define APBW_IDM_IDM_ERROR_LOG_ID 0x18131914
#define APBW_IDM_IDM_ERROR_LOG_FLAGS 0x1813191c
#define APBW_IDM_IDM_INTERRUPT_STATUS 0x18131a00
#define APBX_IDM_IDM_ERROR_LOG_CONTROL 0x18132900
#define APBX_IDM_IDM_ERROR_LOG_COMPLETE 0x18132904
#define APBX_IDM_IDM_ERROR_LOG_STATUS 0x18132908
#define APBX_IDM_IDM_ERROR_LOG_ADDR_LSB 0x1813290c
#define APBX_IDM_IDM_ERROR_LOG_ID 0x18132914
#define APBX_IDM_IDM_ERROR_LOG_FLAGS 0x1813291c
#define APBX_IDM_IDM_INTERRUPT_STATUS 0x18132a00
#define AXIIC_DS_0_IDM_ERROR_LOG_CONTROL 0x18141900
#define AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE 0x18141904
#define AXIIC_DS_0_IDM_ERROR_LOG_STATUS 0x18141908
#define AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB 0x1814190c
#define AXIIC_DS_0_IDM_ERROR_LOG_ID 0x18141914
#define AXIIC_DS_0_IDM_ERROR_LOG_FLAGS 0x1814191c
#define AXIIC_DS_0_IDM_INTERRUPT_STATUS 0x18141a00

#define IHOST_AXITRACE_M1_ATM_CONFIG 0x19004000
#define IHOST_AXITRACE_M1_ATM_CMD 0x1900400c
#define IHOST_AXITRACE_M0_ATM_CONFIG 0x19003000
#define IHOST_AXITRACE_M0_ATM_CMD 0x1900300c
#define IHOST_AXITRACE_ACP_ATM_CONFIG 0x19007000
#define IHOST_AXITRACE_ACP_ATM_CMD 0x1900700c

#define IHOST_SCU_INVALIDATE_ALL 0x1902000c
#define IHOST_SCU_CONTROL 0x19020000
#define IHOST_L2C_CACHE_ID 0x19022000

#define DDR_DENALI_CTL_00 0x18010000
#define DDR_DENALI_CTL_01 0x18010004
#define DDR_DENALI_CTL_03 0x1801000c
#define DDR_DENALI_CTL_04 0x18010010
#define DDR_DENALI_CTL_05 0x18010014
#define DDR_DENALI_CTL_06 0x18010018
#define DDR_DENALI_CTL_07 0x1801001c
#define DDR_DENALI_CTL_08 0x18010020
#define DDR_DENALI_CTL_09 0x18010024
#define DDR_DENALI_CTL_10 0x18010028
#define DDR_DENALI_CTL_11 0x1801002c
#define DDR_DENALI_CTL_12 0x18010030
#define DDR_DENALI_CTL_12_BASE 0x030
#define DDR_DENALI_CTL_13 0x18010034
#define DDR_DENALI_CTL_14 0x18010038
#define DDR_DENALI_CTL_15 0x1801003c
#define DDR_DENALI_CTL_16 0x18010040
#define DDR_DENALI_CTL_17 0x18010044
#define DDR_DENALI_CTL_18 0x18010048
#define DDR_DENALI_CTL_19 0x1801004c
#define DDR_DENALI_CTL_20 0x18010050
#define DDR_DENALI_CTL_21 0x18010054
#define DDR_DENALI_CTL_22 0x18010058
#define DDR_DENALI_CTL_23 0x1801005c
#define DDR_DENALI_CTL_24 0x18010060
#define DDR_DENALI_CTL_25 0x18010064
#define DDR_DENALI_CTL_26 0x18010068
#define DDR_DENALI_CTL_27 0x1801006c
#define DDR_DENALI_CTL_28 0x18010070
#define DDR_DENALI_CTL_29 0x18010074
#define DDR_DENALI_CTL_30 0x18010078
#define DDR_DENALI_CTL_31 0x1801007c
#define DDR_DENALI_CTL_32 0x18010080
#define DDR_DENALI_CTL_35 0x1801008c
#define DDR_DENALI_CTL_36 0x18010090
#define DDR_DENALI_CTL_37 0x18010094
#define DDR_DENALI_CTL_38 0x18010098
#define DDR_DENALI_CTL_39 0x1801009c
#define DDR_DENALI_CTL_40 0x180100a0
#define DDR_DENALI_CTL_41 0x180100a4
#define DDR_DENALI_CTL_42 0x180100a8
#define DDR_DENALI_CTL_43 0x180100ac
#define DDR_DENALI_CTL_44 0x180100b0
#define DDR_DENALI_CTL_45 0x180100b4
#define DDR_DENALI_CTL_46 0x180100b8
#define DDR_DENALI_CTL_47 0x180100bc
#define DDR_DENALI_CTL_48 0x180100c0
#define DDR_DENALI_CTL_49 0x180100c4
#define DDR_DENALI_CTL_50 0x180100c8
#define DDR_DENALI_CTL_51 0x180100cc
#define DDR_DENALI_CTL_52 0x180100d0
#define DDR_DENALI_CTL_53 0x180100d4
#define DDR_DENALI_CTL_54 0x180100d8
#define DDR_DENALI_CTL_55 0x180100dc
#define DDR_DENALI_CTL_56 0x180100e0
#define DDR_DENALI_CTL_57 0x180100e4
#define DDR_DENALI_CTL_58 0x180100e8
#define DDR_DENALI_CTL_59 0x180100ec
#define DDR_DENALI_CTL_60 0x180100f0
#define DDR_DENALI_CTL_61 0x180100f4
#define DDR_DENALI_CTL_62 0x180100f8
#define DDR_DENALI_CTL_63 0x180100fc
#define DDR_DENALI_CTL_64 0x18010100
#define DDR_DENALI_CTL_65 0x18010104
#define DDR_DENALI_CTL_66 0x18010108
#define DDR_DENALI_CTL_67 0x1801010c
#define DDR_DENALI_CTL_68 0x18010110
#define DDR_DENALI_CTL_69 0x18010114
#define DDR_DENALI_CTL_70 0x18010118
#define DDR_DENALI_CTL_71 0x1801011c
#define DDR_DENALI_CTL_72 0x18010120
#define DDR_DENALI_CTL_73 0x18010124
#define DDR_DENALI_CTL_74 0x18010128
#define DDR_DENALI_CTL_75 0x1801012c
#define DDR_DENALI_CTL_76 0x18010130
#define DDR_DENALI_CTL_77 0x18010134
#define DDR_DENALI_CTL_78 0x18010138
#define DDR_DENALI_CTL_79 0x1801013c
#define DDR_DENALI_CTL_80 0x18010140
#define DDR_DENALI_CTL_81 0x18010144
#define DDR_DENALI_CTL_82 0x18010148
#define DDR_DENALI_CTL_83 0x1801014c
#define DDR_DENALI_CTL_84 0x18010150
#define DDR_DENALI_CTL_85 0x18010154
#define DDR_DENALI_CTL_86 0x18010158
#define DDR_DENALI_CTL_87 0x1801015c
#define DDR_DENALI_CTL_88 0x18010160
#define DDR_DENALI_CTL_89 0x18010164
#define DDR_DENALI_CTL_91 0x1801016c
#define DDR_DENALI_CTL_92 0x18010170
#define DDR_DENALI_CTL_93 0x18010174
#define DDR_DENALI_CTL_94 0x18010178
#define DDR_DENALI_CTL_95 0x1801017c
#define DDR_DENALI_CTL_96 0x18010180
#define DDR_DENALI_CTL_97 0x18010184
#define DDR_DENALI_CTL_98 0x18010188
#define DDR_DENALI_CTL_99 0x1801018c
#define DDR_DENALI_CTL_100 0x18010190
#define DDR_DENALI_CTL_101 0x18010194
#define DDR_DENALI_CTL_102 0x18010198
#define DDR_DENALI_CTL_103 0x1801019c
#define DDR_DENALI_CTL_104 0x180101a0
#define DDR_DENALI_CTL_105 0x180101a4
#define DDR_DENALI_CTL_106 0x180101a8
#define DDR_DENALI_CTL_107 0x180101ac
#define DDR_DENALI_CTL_108 0x180101b0
#define DDR_DENALI_CTL_109 0x180101b4
#define DDR_DENALI_CTL_110 0x180101b8
#define DDR_DENALI_CTL_111 0x180101bc
#define DDR_DENALI_CTL_112 0x180101c0
#define DDR_DENALI_CTL_113 0x180101c4
#define DDR_DENALI_CTL_114 0x180101c8
#define DDR_DENALI_CTL_115 0x180101cc
#define DDR_DENALI_CTL_116 0x180101d0
#define DDR_DENALI_CTL_117 0x180101d4
#define DDR_DENALI_CTL_118 0x180101d8
#define DDR_DENALI_CTL_119 0x180101dc
#define DDR_DENALI_CTL_120 0x180101e0
#define DDR_DENALI_CTL_121 0x180101e4
#define DDR_DENALI_CTL_122 0x180101e8
#define DDR_DENALI_CTL_123 0x180101ec
#define DDR_DENALI_CTL_124 0x180101f0
#define DDR_DENALI_CTL_125 0x180101f4
#define DDR_DENALI_CTL_126 0x180101f8
#define DDR_DENALI_CTL_127 0x180101fc
#define DDR_DENALI_CTL_128 0x18010200
#define DDR_DENALI_CTL_129 0x18010204
#define DDR_DENALI_CTL_130 0x18010208
#define DDR_DENALI_CTL_131 0x1801020c
#define DDR_DENALI_CTL_132 0x18010210
#define DDR_DENALI_CTL_133 0x18010214
#define DDR_DENALI_CTL_134 0x18010218
#define DDR_DENALI_CTL_135 0x1801021c
#define DDR_DENALI_CTL_136 0x18010220
#define DDR_DENALI_CTL_137 0x18010224
#define DDR_DENALI_CTL_138 0x18010228
#define DDR_DENALI_CTL_139 0x1801022c
#define DDR_DENALI_CTL_140 0x18010230
#define DDR_DENALI_CTL_141 0x18010234
#define DDR_DENALI_CTL_142 0x18010238
#define DDR_DENALI_CTL_143 0x1801023c
#define DDR_DENALI_CTL_144 0x18010240
#define DDR_DENALI_CTL_145 0x18010244
#define DDR_DENALI_CTL_146 0x18010248
#define DDR_DENALI_CTL_147 0x1801024c
#define DDR_DENALI_CTL_148 0x18010250
#define DDR_DENALI_CTL_149 0x18010254
#define DDR_DENALI_CTL_150 0x18010258
#define DDR_DENALI_CTL_151 0x1801025c
#define DDR_DENALI_CTL_152 0x18010260
#define DDR_DENALI_CTL_153 0x18010264
#define DDR_DENALI_CTL_156 0x18010270
#define DDR_DENALI_CTL_157 0x18010274
#define DDR_DENALI_CTL_158 0x18010278
#define DDR_DENALI_CTL_160 0x18010280
#define DDR_DENALI_CTL_161 0x18010284
#define DDR_DENALI_CTL_162 0x18010288
#define DDR_DENALI_CTL_163 0x1801028c
#define DDR_DENALI_CTL_165 0x18010294
#define DDR_DENALI_CTL_166 0x18010298
#define DDR_DENALI_CTL_167 0x1801029c
#define DDR_DENALI_CTL_168 0x180102a0
#define DDR_DENALI_CTL_169 0x180102a4
#define DDR_DENALI_CTL_170 0x180102a8
#define DDR_DENALI_CTL_171 0x180102ac
#define DDR_DENALI_CTL_172 0x180102b0
#define DDR_DENALI_CTL_173 0x180102b4
#define DDR_DENALI_CTL_174 0x180102b8
#define DDR_DENALI_CTL_175 0x180102bc
#define DDR_DENALI_CTL_176 0x180102c0
#define DDR_DENALI_CTL_177 0x180102c4
#define DDR_DENALI_CTL_178 0x180102c8
#define DDR_DENALI_CTL_179 0x180102cc
#define DDR_DENALI_CTL_180 0x180102d0
#define DDR_DENALI_CTL_181 0x180102d4
#define DDR_DENALI_CTL_182 0x180102d8
#define DDR_DENALI_CTL_183 0x180102dc
#define DDR_DENALI_CTL_184 0x180102e0
#define DDR_DENALI_CTL_185 0x180102e4
#define DDR_DENALI_CTL_186 0x180102e8
#define DDR_DENALI_CTL_187 0x180102ec
#define DDR_DENALI_CTL_188 0x180102f0
#define DDR_DENALI_CTL_189 0x180102f4
#define DDR_DENALI_CTL_190 0x180102f8
#define DDR_DENALI_CTL_191 0x180102fc
#define DDR_DENALI_CTL_192 0x18010300
#define DDR_DENALI_CTL_193 0x18010304
#define DDR_DENALI_CTL_194 0x18010308
#define DDR_DENALI_CTL_195 0x1801030c
#define DDR_DENALI_CTL_197 0x18010314
#define DDR_DENALI_CTL_198 0x18010318
#define DDR_DENALI_CTL_199 0x1801031c
#define DDR_DENALI_CTL_200 0x18010320
#define DDR_DENALI_CTL_201 0x18010324
#define DDR_DENALI_CTL_202 0x18010328
#define DDR_DENALI_CTL_203 0x1801032c
#define DDR_DENALI_CTL_204 0x18010330
#define DDR_DENALI_CTL_206 0x18010338
#define DDR_DENALI_CTL_207 0x1801033c
#define DDR_DENALI_CTL_210 0x18010348
#define DDR_DENALI_CTL_211 0x1801034c
#define DDR_DENALI_CTL_212 0x18010350
#define DDR_DENALI_CTL_213 0x18010354
#define DDR_DENALI_CTL_214 0x18010358
#define DDR_DENALI_CTL_215 0x1801035c
#define DDR_DENALI_CTL_216 0x18010360
#define DDR_DENALI_CTL_217 0x18010364

#define IPROC_QSPI_MEM_BASE		(0x1c000000)
#define IPROC_NAND_MEM_BASE		(0x28000000)
#define IPROC_NOR_MEM_BASE		(0x20000000)

#endif /* __SOCREGS_H */
